Intel outlined three separate chip architectures at Hot Chips 2026 built for agentic AI and enterprise-scale workloads: the Diamond Rapids CPU for high-performance orchestration in the data centre, the Crescent Island GPU for efficient inference, and the Wildcat Lake SoC for client and edge computing. Intel frames the three as stages of one pipeline, where an agent’s reasoning and orchestration run on the CPU, the heavy inference work runs on the GPU, and short, latency-sensitive tasks run locally on the client chip instead of being routed to a data centre.
Diamond Rapids CPU: 256 cores and a new interconnect
The headline number for the Diamond Rapids CPU is scale: up to 256 Panther Cove P-cores per socket, backed by as much as 1.28GB of last-level cache. The core complex chiplets are built on Intel’s 18A-P foundry node, and the package adds PCI-Express Gen 6 and AVX 10.2 instructions. Intel is also switching the chip’s internal interconnect from EMIB to UCIe-S, an open chiplet standard that replaces the proprietary bridge Intel has used on earlier Xeon generations, a change Tom’s Hardware detailed from the Hot Chips session that other write-ups skipped. Diamond Rapids, sold under the Xeon 7 name, is due in the data centre in 2027.
Crescent Island GPU: memory capacity over raw core count
Where Diamond Rapids is built to orchestrate, the Crescent Island GPU is built to run inference cheaply at volume. Intel is offering it with LPDDR5X memory scaling from 160GB up to 480GB, a range aimed at the working-set sizes agentic workloads need rather than at peak throughput. Wildcat Lake, the third chip in the trio, got far less technical detail in Intel’s own materials at this event; it is positioned as the SoC that brings agentic features to client PCs and edge hardware, running smaller models locally rather than sending every request out to a server.
Our take: what the memory range actually means
Intel and the outlets covering Crescent Island report the 160GB to 480GB range as two endpoints, not as a rate of change. By our arithmetic, the top configuration carries three times the memory of the entry one, a 200% increase, not the incremental bump vendors usually ship between GPU tiers. That gap is a bigger signal than a spec sheet line: it tells you Intel expects agentic inference workloads to vary far more in memory footprint than in raw compute, and it is building one architecture configurable across that whole range rather than shipping separate parts for small and large models.
The framing also puts Intel’s three-chip pitch in contrast with rivals showing rack-scale systems at the same event, including AMD’s MI400 Helios architecture and NVIDIA’s Vera Rubin NVL72 rack. Waymo used the same event to detail its own sensor fusion processor, underscoring how much of Hot Chips 2026 was about purpose-built silicon rather than general-purpose chips. Intel’s approach is narrower: three distinct chips, each targeting one stage of an agentic pipeline, rather than one integrated rack-scale platform.
What to watch
Diamond Rapids is not expected in the data centre until 2027, so the figures shown at Hot Chips are architectural targets rather than shipping silicon. The next checkpoints are whether Intel confirms clock speeds and power envelopes for Diamond Rapids, and whether Crescent Island lands named customers before Wildcat Lake reaches client devices.
